This invention relates in general to the field of testing electronic devices, and more particularly to testing memory modules.
Memory integrated circuits are typically assembled on memory modules for incorporation into computing devices, such as personal computers. Before a memory module is incorporated in a computing device, the module and memory integrated circuits assembled on the module are usually tested for faults. For instance, personal computer manufacturers typically purchase memory modules from subcontractors. The subcontractors assemble the memory integrated circuits on the memory modules according to the manufacturers specifications, and then test the modules to ensure their proper operation before shipping the modules to the manufacturer. Computer manufacturers expect high reliability for the memory modules. Thus, subcontractors who assemble memory modules generally must test the assembled modules to meet predetermined specifications of the computer manufacturer with a high degree of reliability.
Conventional memory integrated circuits include DRAM, SDRAM, and SGRAM integrated circuits that operate at speeds of up to 100 megahertz. Recently, a new type of integrated memory circuit known as a direct RAMBUS integrated circuit (RDRAM), has been introduced that is capable of operating at much higher speeds, such as a clock speed of 400 megahertz, with data transactions occurring on both edges of the clock signal to provide an effective device speed of 800 megahertz. To obtain these improved operating speeds, RAMBUS integrated circuits are loaded on a specially designed RDRAM integrated memory module, known as a RAMBUS In-Line Memory Module (xe2x80x9cRIMMxe2x80x9d). RIMMs include a Direct RAMBUS ASIC channel cell (RAC) to support communications between the RIMM and another RAC located in a computing device. A RAC is a logical to physical interface that multiplexes and demultiplexes 144 bit wide datums with an 18 bit wide RAMBUS channel. Cooperating RACs communicate data over the 18 bit wide RAMBUS channel by exchanging control and address information in unique packetized formats. A RAMBUS Memory Controller (xe2x80x9cRMCxe2x80x9d) supports data transfers with a RAC by taking simple high-level commands and data to create simpler commands formatted for the RAC and by scheduling for data transmittal or retrieval.
For instance, a RMC may receive or transmit data at a 100 MHz clock rate. In one clock cycle, the RMC may receive 40 bits worth of information, including 35 address bits, 4 command bits and 1 packet length bit, along with 144 bits worth of data to be written to a RIMM. The RMC reformats the 40 address/command/length bits into a sequence of commands to the RAC with each command having 64 bits of packet information and 12 bits of scheduling information. The 144 bits of data are passed unchanged to the RAC. The RAC then transmits this information to a RAC of one of the Direct RDRAM chips in the RIMM with the 64 bits of packet information broken down into 8 sets of 8 bits and the 144 bits of data broken down into 8 sets of 18 bits. The transfer between RACs is clocked out on the leading and trailing edges of a 400 MHz clock to allow all eight sets of data to be transmitted within a 10ns window that matches the 100 MHz system bus clock.
The use of RDRAM integrated circuits loaded on a RIMM allows a substantial increase in the rate at which data is exchanged for use by a processor of a computing device. However, the increased speed at which RIMMs operate makes it especially important to ensure that no faults exist on the RIMMs before the RIMMs are used in a computing device. At the present time, commercial microprocessor bus systems do not exist that will support a RAMBUS channel operating at higher than 100 megahertz.
Faults associated with a RIMM can be introduced in a number of different manners. A fault can exist in the RDRAM integrated circuits and RIMM printed wire board (PWB) before assembly, or can be introduced during assembly. For instance, RIMM PWBs can have PWB faults such as open or shorted traces due to under plating or over plating, excessive warpage, and out of tolerance electrical characteristics. RDRAM faults can include open or shorted pins due to lead frame bonding flaws, inoperable nodes internal to the device, and excessive sensitivity to signal patterns, temperature variations, voltages, and/or internal node states. Faults introduced during assembly of a RIMM can include incorrect installation of parts, open or shorted signals through the use of excessive or insufficient solder, signal path contamination resulting in high pin leakage, ESD damage resulting in high pin leakage, and damaged pin drivers or input buffers.
Several conventional testers are available for testing memory modules. The simplest type of memory tester is a microprocessor-based tester. Microprocessor-based testers essentially act as a mother board to pass microprocessor-generated test data to a module and read the test data sent back from the module. The memory module is tested by comparing the written and read data. Although microprocessor-based testers are simple to build and use, they are generally slow in operation and incapable of performing more complex types of tests. Such testers usually feature commodity memory controllers as the interface between the microprocessor and the memory module.
Most other types of conventional memory testers are hardware-enhanced. Hardware-enhanced testers provide more rapid testing of memory modules by using specialized hardware to generate test accesses and verify test data. One such hardware-enhanced memory testing system is a vector-based system. Vector-based systems use a microprocessor to generate test data, and then store the test data in memory until the data is sent to the module under test. A key disadvantage to vector-based systems is that they generally require large amounts of memory for storing test data before the data is sent to the module under test.
Another hardware-enhanced method for testing memory modules is through the use of an interface that provides test data to the module under test. For instance, the SIGMA testing systems produced by Tanisys Technology, Inc. create test data with algorithms and incorporate specialized controllers to interface the algorithmically-created data with the module under test. A microprocessor supervises the operation of the specialized controller, which in response generates and writes predetermined data to the memory module through an interface, and then reads back the data and compares it against the written data to ensure that the memory module is operating properly.
Many of the hardware-enhanced memory testers use pin drivers. Pin drivers and receivers interfaced with the memory module send signals to and receive signals from the memory module under test. Conventional pin drivers are frequently used to test a variety of integrated circuits, including microprocessors, where operational parameters such as input voltage range, output voltage range, power supply range, and signal timing vary widely between device types. Pin-driver based testers generally incorporate expensive and complex hardware and software that determine whether the output signals generated are appropriate for a given suite of test signals. Conventional pin drivers are expensive and their use to test memory devices is generally considered overkill since memory devices typically operate over a narrow range of voltages and speeds, such as the 0.8 voltage swing for RDRAM signals, whereas pin drivers are designed to operate over a large voltage range, such as 7 to xe2x88x925 volts. In addition, conventional pin drivers are typically housed in large packages with high input voltages that generate considerable amounts of heat, frequently requiring cooling by fluids.
A number of difficulties exist in attempting to use conventional memory testing systems to test RIMMs. One difficulty is presented by the rapid operating speeds of RIMMs. For instance, conventional 100 megahertz memory devices and busses cannot exchange data at the full operating rate of a RIMM. Although pin-driver systems can present data to a RIMM at full operating speeds, pin driver systems are expensive and difficult to use.
Another difficulty is converting data generated by conventional testing systems into a format that is readable by a RIMM. For instance, RIMMs typically have 8 control lines that carry packetized control information in 64 bit packets. Further, RIMMS have an 18 bit wide RAMBUS channel with occupancy of the channel dependent upon prior and pending channel activity.
Another difficulty is the implementation of testing algorithms and sequences that test the various RIMM configurations and RIMM transaction sequences under worst-case test conditions.
Therefore a need has arisen for a memory testing system and method which will support inexpensive testing of RIMMs with at-speed test data.
A further need has arisen for a memory testing system and method which maintains full utilization of a RAMBUS channel to test the RIMM at full operating speeds.
A further need has arisen for a memory testing system and method which supports testing of a variety of RIMM configurations under a variety of test conditions.
In accordance with the present invention, a memory testing system and method is provided that substantially eliminates or reduces disadvantages and problems association with previously developed memory testing systems and methods. A RIMM adapter accepts test data for transfer to and from a RIMM to allow evaluation of the RIMM""s operation.
The RIMM adapter includes an application specific integrated circuit (ASIC) having a RAC that multiplexes and demultiplexes test data with a RAMBUS channel. The RAMBUS channel is controlled by a channel controller located on board the ASIC in communication with the RAC. The channel controller writes and reads data from one or more first-in-first-out (FIFO) circuits also located on board the ASIC. The FIFOs form the interface between the ASIC of the RIMM adapter and a test transaction engine. In one embodiment, the test transaction engine is a hardware-enhanced based memory tester.
In another embodiment, a test transaction engine located on the RIMM adapter generates and compares test data based on instructions provided to processing circuits, such as field programmable gate arrays. A sequencer in communication with write data generate, address/command generate and read data compare engines supports transfer of test transaction data between the FIFOs and the test transaction engine. The FIFOs allow the RAC to provide the RIMM data transactions at full operating speed. Registers located on the ASIC of the RIMM adapter are in communication with the channel controller and RAC to allow modifications of the operational characteristics of the channel controller and RAC to support control of channel drive strengths and timing. A parametric measurement unit (PMU) and a load unit interface with the RIMM to provide analog testing signals and simulated loads.
Instructions for test data transactions are provided by a host computer in communication with the test transaction engine. The instructions are stored in a SRAM, and identify the type of transactions to be performed with the RIMM. A sequencer communicates with the SRAM and with the host computer, a read compare engine, a write generate engine, and an address command generate engine. The sequencer supplies addresses to the SRAM in a user defined order to have the write generate and address command generate engines generate both transaction address commands and test write data for transfer to the RIMM, or to have the read compare engine verify data returned from the RIMM. Instructions from the SRAM direct the sequencer to modify the address, test write data, and read compare data after a transaction is issued to support a high data flow rate to the RIMM.
The read compare engine and write generate engines have separate data paths for communicating with the RIMM adapter ASIC. The channel controller of the ASIC accepts data from the write generate engine through a write FIFO for transmission to the RIMM as the RAMBUS channel is available, and provides data received from the RAMBUS channel to a read FIFO for transmission to the read compare engine. The read compare engine compares data received from the RIMM with expected data values and issues status results back to the sequencer and host computer.
In one embodiment, the read compare engine, write generate engine and address command generate engine are field programmable gate arrays (FPGAs), having a bank of registers sharing a single arithmetic logic unit to provide interleaved accesses that help ensure uninterrupted data flow to and from the RIMM.
In another embodiment, the RIMM adapter ASIC includes a bypass circuit that allows direct communication between the test transaction engine and the RAC loaded on the ASIC. The bypass mode allows direct communication of test transaction data from the tester to the RAC without processing by the channel controller loaded on the ASIC. Thus, for instance, the test transaction engine may provide 64 bit commands and 144 bit data directly to the RAC on the ASIC to test failure modes in the field with a logic analyzer.
The present invention provides a number of important technical advantages. One important technical advantage is that the RIMM adapter implements transaction sequences for testing a RIMM at full speed when supplied with transaction commands issued by lower-speed testing engines. For instance, 100 megahertz, 144 bit datum transactions are provided to the 18 bit RIMM channel through the RIMM adapter to facilitate full control of transaction sequences. Further, the transactions are not constrained by microprocessor or memory controller implementations.
Another important technical advantage of the present invention is that full utilization of the RIMM channel is maintained. The RIMM channel is tested at full speed, such as its 800 megahertz operating speed, by transactions provided through the RIMM adapter. Separate read and write paths provide double the speed of a single read and write path and avoids waiting for host bus turnaround. Further, by locating a memory controller on board an ASIC instead of in the test engine, and providing test data through FIFO circuits before assigning the test data to memory channels, the time for transferring data to the RIMM is reduced.
Another advantage of the present invention is that it supports a variety of RIMM configurations tested under a variety of conditions. The channel controller supports control of channel drive strengths and timing to adjust data and clock skew. For instance, the channel controller allows testing with different numbers of RDRAM parts loaded on a RIMM, and with delays in clocking rate that may be associated with changes in bus length. The load unit simulates operational conditions to ensure the RIMM meets worst case test conditions, including simulation of multiple RIMMS loaded on a RAMBUS channel.
Another important technical advantage of the present invention is that the test transaction engine may communicate directly with the RAC through the bypass circuit. By configuring the ASIC so that the channel controller is bypassed, all possible memory access methods for talking to the RIMM may be utilized, which allows for- the testing of additional sequences of RAC commands that may cause failures.